1. Field of Invention
The present invention relates generally to chemical mechanical polishing, and more specifically, to the use of utility wafers for simulating chemical mechanical polishing processes.
2. Background of Invention
In semiconductor wafer processing, the use of chemical mechanical planarization, or CMP, has gained favor due to the enhanced ability to stack multiple devices on a semiconductor workpiece, or substrate, such as a wafer. As the demand for planarization of layers formed on wafers in semiconductor fabrication increases, the requirement for greater system (i.e., process tool) throughput with less wafer damage and enhanced wafer planarization has also increased.
Two exemplary CMP systems that address these issues are described in U.S. Pat. No. 5,804,507, issued Sep. 8, 1998, to Perlov et al., and in U.S. Pat. No. 5,738,574, issued Apr. 15, 1998, to Tolles et al., both of which are hereby incorporated by reference. Perlov et al. and Tolles et al. disclose a CMP system having a planarization apparatus that is supplied wafers from cassettes located in an adjacent liquid filled bath. A transfer mechanism, or robot, facilitates the transfer of the wafers from the bath to a transfer station. The transfer station generally contains a load cup that positions the wafer into one of four processing heads mounted to a carousel. The carousel moves each processing head sequentially over the load cup to receive a wafer. As the processing heads fill, the carousel moves the processing head and wafer through the planarization stations for polishing. The wafers are planarized by moving the wafer relative to a polishing pad in the presence of a slurry or other polishing fluid medium.
The polishing pad may include an abrasive surface. Additionally, the slurry may contain both chemicals and abrasives that aid in the removal of material from the wafer. After completion of the planarization process, the wafer is returned back through the transfer station to the proper cassette located in the bath.
The ideal substrate polishing process can be described by Preston""s equation:   R  =            K      P        ⁢    P    ⁢                  Δ        ⁢                  xe2x80x83                ⁢        s                    Δ        ⁢                  xe2x80x83                ⁢        t            
where:
R is the removal rate;
Kp is the Preston coefficient;
P is the applied pressure between the workpiece and the abrasive pad; and
xcex94s/xcex94t is the linear velocity of the abrasive pad relative the workpiece.
Preston""s equation has shown to be a reasonably accurate model for the planarization of silicon dioxide, copper and tungsten, although the dependence of Kp on process variables, such as slurry composition and pad properties, is not well understood. For example, the theoretical value of the Preston coefficient Kp=1/2E (where E is Young""s modulus of the surface being polished) does not explain the polishing rate variation with other important process variables such as pad type, pad condition, slurry abrasive and slurry chemicals. Illustrative of this is that the polishing rate has been known to vary as much as 20 percent between pads having different hardness. As a result, most chemical mechanical polishing process modeling is performed using empirical data.
To better predict the results of an actual chemical mechanical polishing process, typically a simulation of the processes is performed using utility wafers in the place of production wafers. Generally, the simulation comprises running a number of utility wafers through the chemical mechanical polishing system, while periodically inserting and polishing a test wafer from which the polishing attributes can be obtained to construct a model of the polishing process. For example, in an exemplary CMP simulation, approximately 2000 polishing cycles are run. After every 100 utility wafers that are polished, a test wafer is polished, removed and measured to obtain data indicative the process. Once approximately 2,000 polishing cycles are completed, a data base representative of the process can be constructed. Other simulations may be configured to run more or less polishing cycles, and may polish test wafers at different frequencies.
The utility wafers typically used to simulate the polishing of the production wafers generally are silicon wafers covered with a thin layer of oxide. Generally, the oxide layer can only withstand one to two polishing cycles through the chemical mechanical polishing system. The utility wafer, once the oxide has been substantially removed by polishing, can be reused after being stripped of the remaining oxide coating and a new layer of oxide is redeposited thereon. As the cost of depositing an oxide layer is not nominal, simulation tests that use between 1,500-2,000 utility wafers can become quite costly.
One solution to the high cost of the oxide coated silicon wafers is described in U.S. Pat. No. 5,890,951, issued Apr. 6, 1999, to Cuong van Vu. Cuong van Vu teaches a utility wafer used for mechanically conditioning and stabilizing a polishing pad. This utility wafer is comprised of a high purity solid ceramic or metal member that has a thickness of between about 3-150 mils. The thickness of the Cuong van Vu utility wafer provides some resistance to breaking when the wafer is exposed to the forces applied in a chemical mechanical planarization process. For example, Cuong van Vu teaches a quartz wafer thickness of 50 mils, and a silicon/quartz composite wafer that can withstand the surface tension forces experienced during the removal of the polished wafer from the polishing pad (dechucking) without breaking or cracking the wafer.
However, ceramic wafers of this type are prone to chipping as the edge of the wafer contacts the retaining ring of the polishing head during the planarization process, during dechucking from the polishing pad, or during handling in general. As the wafer contacts the retaining ring, pieces of material break off from the corners and stress cracks tend to propagate from the chipped edges as the wafer contacts against the retaining ring. These chips and cracks generally lead to premature failure of the utility wafer.
Therefore, there is a need in the art for a utility wafer that provides a durable, low cost means for simulating a wafer in a chemical mechanical polishing system.
In one aspect, a utility wafer is provided which generally includes a first side and a second side opposing the first side and defining a thickness therebetween. A peripheral edge couples the first side and the second side. An edge defined at the interface of the peripheral edge and the first side is relieved, i.e., the edge has a chamfer, radius or other relief. Optionally, a second edge at the interface of the peripheral edge and the second side is also relieved. In another embodiment, the peripheral edge is polished.
In another aspect, a method for fabricating a utility wafer is provided. The method generally comprises providing a wafer having a thickness of at least about 45 mils relieving at least one edge of the wafer and polishing the wafer. In one embodiment the wafer is laser polished and annealed.